Pertech is the authorized Prodigy distributor. The range covers protocol exercisers and analyzers for storage interfaces (UFS, eMMC, SD/SDIO, UHS-II, PCIe and QSPI), mobile interfaces (I3C and RFFE) and embedded buses (MDIO, I2C and SPI), plus decode and electrical validation software that runs on an oscilloscope.

An oscilloscope shows the electrical signal: voltage levels, edges, noise and timing margins. That is the right view when the fault is in the physical layer, and Prodigy's oscilloscope-based software adds protocol decode and electrical measurements to Tektronix scopes for exactly that job.

A dedicated protocol analyzer is built for the layers above the signal. It decodes every packet in hardware as it arrives, triggers on protocol events such as a specific command, an error or a state change, and records far longer than a scope's capture memory: the I3C analyzer streams continuously to the host disk and the PCIe analyzer stores up to 64 GB. For a bug that shows up once in millions of transactions, or on links as fast as UFS 5.0 at 46.64 Gbps per lane and PCIe Gen5, that depth and protocol-level view is what finds the fault. Many teams use both: the scope for signal integrity, the analyzer for protocol behavior.

An exerciser takes the place of a device on the bus and generates traffic you control. Engineers use it to:

• Emulate a controller, host, target or device that is not available yet, so firmware and silicon can be tested before the rest of the system exists
• Send exact command sequences and timing that are hard to reproduce with real devices
• Inject protocol errors and check that the device under test detects them and recovers
• Run conformance and regression tests from scripts

Prodigy's I3C exerciser, for example, injects protocol errors and runs MCTP, NVMe-MI and SPDM conformance tests, and the UFS 5.0 model can emulate a UFS host or device.

Together they close the loop: the exerciser asks the question and the analyzer records the answer. A typical flow:

1. Emulate the missing side of the link with the exerciser, a controller to test a target or the other way round.
2. Run a scripted sequence: clean traffic first, then corner cases such as timing variations, unusual command orders and injected errors.
3. Capture the bus with the analyzer, triggered on the stimulus or on any protocol error, and read the decoded response layer by layer.
4. Compare the response with the specification, fix the firmware or design, and rerun the same script to confirm.

Because the stimulus is repeatable and the capture is decoded, intermittent faults become reproducible, and the script becomes a regression test for every new build. Prodigy's I3C and UFS 5.0 tools combine both functions in one unit, so you drive a transaction and capture the result in the same session.

I3C is the MIPI Alliance serial bus that succeeds I2C for connecting sensors and other peripherals to a processor. It runs at up to 12.5 MHz and adds in-band interrupts (IBI) and Hot-Join. Beyond mobile phones it is being adopted in automotive, DDR5 memory, SSD, CXL and PMIC designs, and DMTF uses it to carry MCTP with NVMe-MI, SPDM and PLDM.

The PGY-I3C-EX-PD acts as a controller and/or target (1 controller and 3 targets, or a secondary controller and 2 targets) to generate I3C and I2C traffic at SCL rates from 1 Hz to 12.5 MHz, with drive levels from 0.9 V to 3.4 V. It injects errors, runs MCTP, NVMe-MI and SPDM conformance tests, decodes I3C and I2C packets while streaming captures continuously to the host, and can be automated from Python or C++. It is upgradeable to dual and quad lane I3C. For firmware and field work there is the portable I3C Lite, and for scripted production test the I3C USB Adapter.

Choose by UFS version and speed. The UFS 4.0/4.1 analyzer decodes M-PHY, UniPro and UFS layers on two lanes from PWM G1 to HS‑G5B. The new UFS 5.0 Protocol Exerciser and Analyzer (PGY-UFS5.0-EX-PA) covers UFS 2.x to UFS 5.0 up to HS‑G6B, 46.6 Gbps per lane with PAM4 signaling, with a 16 GB capture buffer upgradable to 32 GB and optional UFS 5.0 host and device emulation.

The PCIe Protocol Analyzer captures PCIe Gen1 to Gen5 at 2.5 to 32 GT/s on four or eight lanes. It decodes TLP and DLLP packets with LTSSM analysis and NVMe decode, triggers in hardware on TS1, TS2, TLP and DLLP contents, and stores traces in a 16 GB buffer expandable to 64 GB. An M.2 interposer is standard, with CEM, U.2, E1.S and SD Express interposers as options.

Yes. The SD, SDIO, eMMC Protocol Analyzer captures and decodes bus traffic, the SoC-based eMMC/SD tester and SD, eMMC AC/DC tester exercise and test devices, and the UHS-II Protocol Analyzer covers UHS-II SD cards.

It is software that runs inside Windows-based Tektronix oscilloscopes and turns the captured waveforms into protocol decode and, for many buses, electrical measurements against the specification at the click of a button. For example, I3C Electrical Validation Software (PGY-I3C-EV) works with Tektronix DPO5000, TDS7000, DPO/DSA/MSO7000 and MSO5/6 series oscilloscopes, and versions are available for eMMC, SD/SDIO, QSPI and MIPI M-PHY/UFS.

Pertech is the authorized Prodigy distributor. Prodigy offers evaluation units, free online technical support and free software updates. Contact Pertech for a quote, a demo, or help choosing the right analyzer for your interface.