The USB-ML-UNIVERSAL extends the same USB-powered debug-probe architecture as the ACP to PEmicro’s full universal device list — ARM Cortex-M plus NXP’s 8-/16-/32-bit legacy families, ColdFire, Power Architecture, DSC, and STMicroelectronics SPC5 — with pipelined programming algorithms for select Power Architecture families and automatic clock-frequency detection for HCS08 and HC(S)12(X) targets. It’s the debug probe to reach for when a bench, or a company’s product line, spans more than just current ARM silicon.
Highlights
- Full universal device coverage on one probe — ARM Cortex-M, NXP 8-/16-/32-bit legacy families, ColdFire V1-V4, Power Architecture, DSC, and STMicroelectronics SPC5
- Pipelined programming algorithms speed up flash programming for select Power Architecture families beyond what a generic JTAG/BDM write achieves
- Auto-frequency detection and trimming for HCS08, and auto-frequency detection for HC(S)12(X), remove manual clock setup from debug and programming sessions
- Generates programming voltage directly on the RESET line for RS08 targets, a requirement the ACP’s ARM-only design doesn’t need to handle
- Same real-time SWO debug features (ITM console, SWO data, real-time expressions) as the ACP, extended across every supported architecture
Where it earns its keep
- Engineering teams whose product line spans both current ARM MCUs and legacy NXP 8-/16-bit designs, who’d rather standardize on one debug probe than stock two
- Bring-up and validation on ColdFire, Power Architecture, or DSC-based boards where the ACP’s ARM-only scope doesn’t apply
- Bench debug work that moves between architectures through the week — one Multilink Universal covers what would otherwise need an ACP plus a separate legacy-device probe
Key Specifications
| Spec | Value |
|---|---|
| Device support | ARM Cortex-M + NXP 8-/16-/32-bit universal families |
| Target voltage range | 1.8V – 5.25V |
| Target power supplied | No (target-powered only) |
| Communications | USB 2.0 |
| SWO / real-time features | ITM console, SWO data, real-time expressions |
| Programming speed | Moderate, with pipelined algorithms for select Power Architecture families |








