ASSET InterTech ScanWorks Boundary-Scan Test applies IEEE 1149.1 and 1149.6 boundary scan (JTAG) to test, diagnose and program circuit boards in development, manufacturing and repair. Tests are model-based and generated from the board netlist, so interconnect, pull-up and pull-down, memory and cluster tests are ready in minutes, and failures are reported down to the pin and net. The same tests and programming flows move from the lab to the production line and to contract manufacturers without changes. Pertech is an ASSET InterTech distributor.
ScanWorks highlights
- Model-based, automatic test generation for IEEE 1149.1 and 1149.6 nets
- Interconnect, pull-up/pull-down, memory (DDR, SRAM and more), cluster and scripted tests
- Diagnostics to the failing pin and net, with a graphical board view
- In-system programming of NOR and NAND flash, SPI and I2C PROMs, FPGAs and CPLDs (IEEE 1532, SVF, STAPL)
- Design browser that imports CAD and schematic data from many vendors
- Runs from its GUI or from any test executive or language through APIs
- Controllers on USB, Ethernet, PCIe, PCI and PXI; delay compensation on Ethernet and PCIe
- IJTAG (IEEE 1687) instrument access and an ICL/PDL validator
Development, production and repair
Engineers build and debug tests with a developer license. Operators run the finished test plans with an operator license: the job folder carries its own library of BSDL files, package definitions and scripts, so a program built in one site runs unchanged at a contract manufacturer. Operator mode lets technicians run the full sequence, a group of tests or a single test, and saving changes requires a developer password. ScanWorks can also share the work with in-circuit, flying-probe and functional testers.
Where ScanWorks fits
- Structural test of dense boards with few test points
- Production test and programming lines and contract manufacturers
- Repair stations diagnosing returned boards
- SoC and board teams reusing embedded instruments through IJTAG
Key Specifications
| Spec | Value |
|---|---|
| Standards | IEEE 1149.1, IEEE 1149.6, IEEE 1687 (IJTAG), IEEE 1532 |
| Tests | Scan path, interconnect, pull-up/pull-down, memory, cluster, flash, I2C, SPI, scripted |
| Programming | NOR/NAND flash, SPI and I2C PROMs, FPGAs, CPLDs; SVF, STAPL, SREC, HEX |
| Diagnostics | Failing pins and nets (opens, shorts), graphical board view |
| Controllers | USB, Ethernet, PCIe, PCI, PXI; TCK up to 50 MHz; I/O 0.8 to 3.3 V (5 V) |
| Integration | APIs for test executives and programming languages; works alongside ICT, MDA, flying-probe and functional testers |
| Licenses | Developer and operator; perpetual, with optional annual support and maintenance |
| Host | Windows 32/64-bit |
Frequently asked questions
What is ScanWorks Boundary-Scan Test?
It is ASSET InterTech’s boundary-scan (JTAG) software for testing, diagnosing and programming circuit boards, based on IEEE 1149.1 and 1149.6.
Which tests does it run?
Scan path integrity, interconnect, pull-up and pull-down, memory, cluster tests of non-boundary-scan devices, and scripted tests for any device reachable through boundary-scan pins.
How precise are the diagnostics?
ScanWorks reports the failing pins and nets, such as opens and shorts, and shows them on a graphical view of the board.
Can it program devices on the board?
Yes: NOR and NAND flash, SPI and I2C PROMs, FPGAs and CPLDs, using IEEE 1532, SVF, STAPL and other formats.
How is it licensed?
Developer licenses create and edit tests; operator licenses run them in production. Licenses are perpetual, with optional annual support and maintenance for updates.
Where can I buy ScanWorks in Israel?
Pertech is an ASSET InterTech distributor in Israel. Contact Pertech for a quote, a demo or an evaluation, or to check that your platform and debug header are supported.
Related ASSET InterTech products at Pertech
Adding boundary scan to your test line? Contact Pertech for a quote, a demo or an evaluation.
