Quick answer: which I3C debug tool do you need?
To see what is happening on an I3C bus, start with a protocol analyzer that captures and decodes I3C traffic. To test a controller or target, or to work before all the hardware exists, add an exerciser or host adapter that can act as an I3C controller or target. For timing problems and signal-integrity questions, use oscilloscope-based decoding and electrical validation software. Pertech supplies all of these in Israel; see the full list on our I3C protocol analyzers and debug solutions page.
MIPI I3C at a glance
| Feature | MIPI I3C | I2C (for comparison) |
|---|---|---|
| Wires | 2 (SCL, SDA) | 2 (SCL, SDA) |
| Default data rate | SDR up to 12.5 MHz (12.5 Mbps raw) | Typically 100 kHz to 1 MHz (3.4 MHz in High-speed mode) |
| High Data Rate modes | HDR-DDR, HDR-Ternary, HDR-BT (about 33 Mbps raw in HDR-Ternary) | None |
| Signalling | Open-drain for the address header, then push-pull | Open-drain |
| Addressing | Dynamic 7-bit addresses assigned by the controller | Static addresses |
| Interrupts | In-band interrupts (IBI) over SDA | No built-in interrupts (usually a separate pin) |
| Clock stretching | Not allowed | Allowed |
Why is I3C harder to debug than I2C?
MIPI I3C keeps the two-wire SCL/SDA bus of I2C but adds features that a standard I2C analyzer does not decode:
- Higher speeds and HDR modes: the default SDR mode runs at up to 12.5 MHz. Optional High Data Rate modes (HDR-DDR, HDR-Ternary and HDR-BT) raise throughput further, to about 33 Mbps raw in HDR-Ternary.
- Push-pull signalling: SDA starts in open-drain mode for the arbitrable address header, then switches to push-pull for data. The controller drives SCL, and clock stretching is not allowed.
- Dynamic addressing: the controller assigns 7-bit dynamic addresses at start-up (ENTDAA, SETDASA or SETAASA), using each target’s 48-bit Provisioned ID.
- In-band interrupts (IBI) and Hot-Join: targets request attention over SDA instead of a separate interrupt pin, with address arbitration deciding who goes first.
- Common Command Codes (CCCs): bus-management commands sent either as broadcast (codes 0x00-0x7F) or direct to one target (0x80-0xFE).
- Mixed I3C/I2C buses: legacy I2C targets can share the bus if they have a 50 ns spike filter and do not stretch the clock (Fast-mode and Fast-mode Plus). Legacy I2C controllers are not supported.
I3C or I3C Basic? I3C Basic is the royalty-free subset of I3C. Version 1.0 supports SDR mode only; later versions add some optional HDR features. Check which version your devices and your debug tool support.
What types of I3C debug tools are there?
Protocol analyzers
Capture bus traffic and decode it into readable transactions, CCCs and IBIs, so you can see what the controller and targets actually sent. Options: the Prodigy I3C Protocol Analyzer and Exerciser (PGY-I3C-EX-PD, decodes I3C and I2C with protocol-aware triggering), the Binho I3C Basic Protocol Analyzer, and the I3C Basic protocol analyzer plugin for Saleae Logic if you already own a Saleae logic analyzer.
Exercisers and host adapters
Act as an I3C controller or target to generate traffic, emulate devices that are not available yet, and test how your design responds. Options:
- Prodigy PGY-I3C-EX-PD: controller or target emulation, CCC, IBI and Hot-Join support, error injection (including S0-S5 errors and HDR-DDR CRC errors), voltage and timing margin testing, and an optional compliance test script package.
- Acute PX2816B Protocol Exerciser: master or slave operation for I2C, I3C, SPI and UART, with a Python scripting interface.
- Binho Supernova: a USB host adapter that works as an I3C Basic controller or target in SDR mode, with IBI, Hot-Join and CCC support, plus I2C, SPI, UART and GPIO.
Oscilloscope-based decoding
Decode I3C directly on a Tektronix oscilloscope so you can see protocol packets and analog waveforms together, which helps with glitches, ringing and timing issues. Option: Prodigy I3C Protocol Trigger & Decode Software (PGY-I3C-PD), which decodes SDR and HDR (DDR, TSL, TSP) traffic and adds a protocol-aware trigger on supported models.
Electrical validation
Measure timing parameters such as clock frequency, high and low periods, rise and fall times, and setup and hold times, and compare them with the I3C specification limits in open-drain, push-pull and legacy I2C modes. Option: Prodigy I3C Electrical Validation Software, which runs on Tektronix oscilloscopes and generates test reports.
How do you choose the right I3C debug tool?
| Tool type | What it does | Best for | Pertech options |
|---|---|---|---|
| Protocol analyzer | Captures and decodes I3C/I2C traffic, CCCs and IBIs | Firmware bring-up and debugging | Prodigy PGY-I3C-EX-PD, Binho I3C Basic analyzer, Saleae I3C Basic plugin |
| Exerciser / host adapter | Acts as an I3C controller or target and generates traffic | Developing controllers or targets, testing before hardware exists, error injection | Prodigy PGY-I3C-EX-PD, Acute PX2816B, Binho Supernova |
| Oscilloscope-based decoding | Decodes I3C on a Tektronix oscilloscope next to the analog waveforms | Glitches, ringing and timing problems | Prodigy PGY-I3C-PD |
| Electrical validation | Measures timing parameters against I3C specification limits | Design validation and compliance | Prodigy I3C Electrical Validation Software |
- Firmware bring-up and debugging: start with a protocol analyzer.
- Developing a controller or target, or testing before hardware exists: add an exerciser or host adapter.
- Intermittent failures or signal-integrity questions: use oscilloscope-based decoding.
- Design validation and compliance: add electrical validation software and exerciser-based error injection.
Frequently asked questions
What is an I3C protocol analyzer?
An I3C protocol analyzer connects to the SCL and SDA lines, captures bus traffic and decodes it into readable transactions, including Common Command Codes (CCCs), in-band interrupts and dynamic address assignment. Engineers use it to see exactly what the controller and targets sent when debugging firmware or hardware.
Can I use an I2C analyzer to debug I3C?
Only partly. An I2C analyzer can show I2C traffic on a mixed bus, but it does not decode I3C features such as dynamic address assignment, CCCs, in-band interrupts or HDR modes, and it may not keep up with the 12.5 MHz SDR clock. For I3C work you need an analyzer that supports I3C.
What is the difference between I3C and I3C Basic?
I3C Basic is the royalty-free subset of the MIPI I3C specification. Version 1.0 of I3C Basic supports the SDR mode only; later versions add some optional HDR features. Check which version your devices and your debug tool support.
Can I2C devices work on an I3C bus?
Yes, legacy I2C target devices can share an I3C bus if they have a 50 ns spike filter and do not stretch the clock, in Fast-mode or Fast-mode Plus. Legacy I2C controllers are not supported on an I3C bus.
What is the difference between an I3C protocol analyzer and an exerciser?
A protocol analyzer listens to the bus and decodes traffic. An exerciser actively drives the bus as an I3C controller or target, so it can generate traffic, emulate missing devices and inject errors. Some tools, such as the Prodigy PGY-I3C-EX-PD, do both.
Where can I buy I3C debug tools in Israel?
Pertech Embedded Solutions supplies I3C protocol analyzers, exercisers, host adapters and oscilloscope software from Prodigy Technovations, Binho and Acute in Israel, with local sales and technical support.
Get help choosing an I3C tool
Pertech’s engineers can help you match a tool to your project, arrange evaluations and provide local support in Israel. See all options on the I3C debug solutions page or contact us.
