UFS Protocol Analyzer
UFS Protocol Analyzer (PGY-UFS3.X-PA) is the Protocol Analyzer with multiple features to capture and debug communication between the host and design under test. PGY-UFS3.X-PA, UFS Protocol Analyzer, a value-based analyzer in its class, offers capture and debugging of data across MPHY, UniPro, and UFS protocol layers. It allows for instantaneous decoding of the UFS layer, UniPro layer, and MPHY layer with the flexibility to correlate decoded data across these protocol layers.
PGY-UFS3.X-PA Supports PWMG1 to HSG4B data rates and two TX, and two RX lane decode. The active probe has minimum electrical loading on the device under test (DUT) and captures protocol data without affecting the performance of the DUT. PGY-UFS3.X-PA protocol Analyzer can support two-lane data. Comprehensive decoding UniPro & UFS on the Fly enables validation of communication between host and device.
PGY-UFS3.X-PA, UFS Protocol Analyzer allows Design and Test Engineers to obtain deep insight into UFS host and device communication. MPHY/UniPro/UFS packet-based triggering allows specific protocol data capture and analysis. PGY-UFS3.X-PA Protocol analyzer instantaneously provides decoding of the UFS layer, UniPro layer, and MPHY layer with a correlation to MPHY, UniPro, and UFS layer.
What are the key features of the UFS Protocol Analyzer?
- Supports version MPHY 4.0, UniPro 1.8, and UFS version 2.1/3.1
- Supports PWM G1 to G7 and HS G1, 2, 3, 4 A and B Series · Supports one/two data lanes (2 TX and 2 RX)
- Flexibility to capture very large data using continuous streaming of Protocol data to host computer
- Hardware-based circular buffer
- Flexibility to decode selected data from an 8GB buffer
- Solder down active probe provides high signal fidelity
- Decoding at MPHY, UniPro, and UFS layer
- Trigger-based on MPHY, UniPro, and UFS layer packet content
- Supports triggering in PWM and HS data rate speeds
- Trigger out a signal at the trigger event allows the triggering of other instruments such as an oscilloscope
- Interface to host system using USB 3.0 or Gigabit Ethernet Interface
- Flexibility to upgrade the hardware firmware using the GbE interface provides easy field up-gradation of FPGA firmware
- Decoded data packets can be exported to a text file for further analysis
- PGY-UFS 3.0-PA Protocol Analyzer is lightweight and can be deployed for on-site/ field tests
