I3C Protocol Analyzer & Exerciser (PGY-I3C-EX-PD) for Design Validation

EAN: PGY-I3C-EX-PD

description

I3C Protocol Analyzer and Exerciser

 

 

 

I3C Protocol Analyzer (PGY-I3C-EX-PD) is the Protocol Analyzer with multiple features to capture and debug communication between host and design under test. I3C Serial bus interface is emerging as a chosen interface for all future sensor connectivity in mobile phone and automotive industries. This could also be chosen as a low-cost, reliable interface for future embedded electronic applications to address the new data-intensive applications.

The PGY-I3C-EX-PD is the leading instrument that enables the design and test engineers to test the I3C designs for their specifications by configuring the PGY-I3C-EX-PD as Master/Slave to generate I3C traffic with error injection capabilities and to decode I3C protocol packets.

 

What are the key features of the I3C Protocol Analyzer and Exerciser?

  • Supports v1.0/v1.1/v1.1.1 Specifications*.
  • Ability to configure it as Master and/or Slave.
  • Ability to configure BCR, LVR, and DCR registers.
  • Simultaneously generate I3C traffic and Protocol decode of the Bus.
  • Optional Compliance Test Specifications (CTS) test script support.
  • Optional support of MCTP Protocol Exerciser and Analyzer over I3C for advanced management and control protocol analysis. View application note [here].
  • Supports legacy I2C slaves and masters.
  • Generate different I3C SDR and HDR Packets.
  • Supports IBI and Hot Plug capabilities.
  • Error Injection such as CRC errors, parity errors, and ACK/NACK errors.
  • Variable I3C data speeds and duty cycle.
  • PMIC device support as per JEDEC DDR5 spec requirement.
  • Margin test capability: Voltage and timing variation.
  • Continuous streaming of protocol data between the instrument and host computer.
  • Timing diagram of Protocol decoded bus.
  • Listing view of Protocol activity.
  • Error Analysis in Protocol Decode.
  • Ability to write exerciser script to combine multiple data frame generation at different data speeds.
  • USB2/3 host computer interface.
  • API support for automation in Python or C++.

*v1.1/v1.1.1 supports only one-lane commands

 

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Frequently Asked Questions

1 What is the primary function of the PGY-I3C-EX-PD I3C Protocol Analyzer and Exerciser?

The PGY-I3C-EX-PD is designed to capture and debug communication between a host and a design under test. It enables design and test engineers to validate I3C designs by generating I3C traffic with error injection capabilities and decoding protocol packets.

2 What I3C specifications does the PGY-I3C-EX-PD support, and is it compatible with I2C?

The PGY-I3C-EX-PD supports I3C Specifications v1.0, v1.1, and v1.1.1. Additionally, it offers backward compatibility by supporting legacy I2C slaves and masters, making it versatile for mixed-protocol environments.

3 How does the PGY-I3C-EX-PD assist in debugging and validating I3C designs?

It assists by simultaneously generating I3C traffic and decoding bus protocols, providing a timing diagram and listing view of activity. It also features error injection capabilities for CRC, parity, and ACK/NACK errors, along with error analysis in protocol decode to identify issues.

4 Does the I3C Protocol Analyzer support automation and advanced testing features?

Yes, it supports automation through API support for Python or C++, allowing users to write exerciser scripts. It also offers optional Compliance Test Specifications (CTS) test script support and optional MCTP Protocol Exerciser and Analyzer for advanced management and control protocol analysis.

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